SAB80515 Datasheet, PDF (120/270 Pages) Siemens Semiconductor Group – 8-Bit Single-Chip Microcontroller Family

Interrupt System
All of these bits that generate interrupts can be set or cleared by software, with the same result as
if they had been set or cleared by hardware. That is, interrupts can be generated or pending
interrupts can be cancelled by software. The only exceptions are the request flags IE0 and lE1. lf
the external interrupts 0 and 1 are programmed to be level-activated, IE0 and lE1 are controlled by
the external source via pin INT0 and INT1, respectively. Thus, writing a one to these bits will not set
the request flag IE0 and/or lE1. In this mode, interrupts 0 and 1 can only be generated by software
and by writing a 0 to the corresponding pins INT0(P3.2) and INT1(P3.3), provided that this will not
affect any peripheral circuit connected to the pins.
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit
in the special function registers IEN0 and IEN1 (figures 8-2 and 8-3). Note that IEN0 contains also
a global disable bit, EAL, which disables all interrupts at once. Also note that in the SAB 8051 the
interrupt priority register IP is located at address 0B8H; in the SAB 80(C)515/80(C)535 this location
is occupied by register IEN1.
8.2 Priority Level Structure
As already mentioned above, all interrupt sources are combined as pairs;
table 8-1 lists the structure of the interrupt sources.
Table 8-1
Pairs of Interrupt Sources
External Interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
Timer 2 interrupt
A/D Converter Interrupt
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
Each pair of interrupt sources can be programmed individually to one of four priority levels by setting
or clearing one bit in the special function register IP0 and one in IP1 (figure 8-7). A low-priority
interrupt can be interrupted by a high-priority interrupt, but not by another interrupt of the same or
a lower priority. An interrupt of the highest priority level cannot be interrupted by another interrupt
source.
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