SAB80515 Datasheet, PDF (117/270 Pages) Siemens Semiconductor Group – 8-Bit Single-Chip Microcontroller Family

Interrupt System
The serial port interrupt is generated by a logical OR of flag RI and Tl in SFR SCON (see
figure 7-7). Neither of these flags is cleared by hardware when the service routine is vectored too.
In fact, the service routine will normally have to determine whether it was the receive interrupt flag
or the transmission interrupt flag that generated the interrupt, and the bit will have to be cleared by
software.
The timer 2 interrupt is generated by the logical OR of bit TF2 in register T2CON and bit EXF2 in
register IRCON. Figures 8-5 and 8-6 show SFR’s T2CON and IRCON. Neither of these flags is
cleared by hardware when the service routine is vectored to. In fact, the service routine may have
to determine whether it was TF2 or EXF2 that generated the interrupt, and the bit will have to be
cleared by software.
Figure 8-4
Special Function Register TCON (Address 88H)
8FH 8EH C5H 8CH 8BH
88H TF1 TR1 TF0 TR0 IE1
8AH
IT1
89H
IE0
88H
IT0
TCON
These bits are not used for interrupt control.
Bit
Function
IT0
Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low-
level triggered external interrupts.
IE0
Interrupt 0 edge flag. Set by hardware when external interrupt edge is detected.
Cleared when interrupt processed.
IT1
Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low-
level triggered external interrupts.
IE1
Interrupt 1 edge flag. Set by hardware when external interrupt edge is detected.
Cleared when interrupt processed.
TF0
Timer 0 overflow flag. Set by hardware on timer/counter overflow. Cleared by
hardware when processor vectors to interrupt routine.
TF1
Timer 1 overflow flag. Set by hardware on timer/counter overflow. Cleared by
hardware when processor vectors to interrupt routine.
The A/D converter interrupt is generated by IADC in register IRCON (see figure 8-6). lt is set
some cycles before the result is available. That is, if an interrupt is generated, in any case the
converted result in ADDAT is valid on the first instruction of the interrupt service routine (with
respect to the minimal interrupt response time). lf continuous conversions are established, IADC is
set once during each conversion. lf an A/D converter interrupt is generated, flag IADC will have to
be cleared by software.
Semiconductor Group
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