SAB80515 Datasheet, PDF (243/270 Pages) Siemens Semiconductor Group – 8-Bit Single-Chip Microcontroller Family

Device Specifications
Watchdog Timer
This feature is provided as a means of graceful recovery from a software upset. After an
external reset, the watchdog timer is cleared and stopped. It can be started and cleared by
software, but it cannot be stopped during active mode of the device. If the software fails to clear
the watchdog timer at least every 65532 machine cycles (about 65 ms if a 12 MHz oscillator
frequency is used), an internal reset will be initiated. The reset cause (external reset or reset
caused by the watchdog) can be examined by software. To clear the watchdog, two bits in two
different special function registers must be set by two consecutive instructions (bits IEN0.6 and
IEN1.6). This is done to prevent the watchdog from being cleared by unexpected opcodes.
It must be noted, however, that the watchdog timer is halted during the idle mode and power-
down mode of the processor (see section "Power Saving Modes" below).
Therefore, it is possible to use the idle mode in combination with the watchdog timer function.
But even the watchdog timer cannot reset the device when one of the power saving modes has
been is entered accidentally.
For these reasons several precautions are taken against unintentional entering of the power-
down or idle mode (see below).
Power Saving Modes
The ACMOS technology of the SAB 80C515 allows two new power saving modes of the device:
The idle mode and the power-down mode. These modes replace the power-down supply mode
via pin V_PD of the SAB 80515 (NMOS). The SAB 80C515 is supplied via
pins V_CC also during idle and power-down operation.
However, there are applications where unintentional entering of these power saving modes
must be absolutely avoided. Such critical applications often use the watchdog timer to prevent
the system from program upsets. Then accidental entering of the power saving modes would
even stop the watchdog timer and would circumvent the watchdog timer’s task of system
protection.
Thus, the SAB 80C515 has an extra pin that allows it to disable both of the power saving
modes. When pin PE is held high, idle mode and power-down mode are completely disabled
and the instruction sequences that are used for entering these modes (see below) will NOT
affect the normal operations of the device. When PE is held low, the use of the idle mode and
power-down mode is possible as described in the following sections.
Pin PE has a weak internal pullup resistor. Thus, when left open, the power saving modes are
disabled.
The Special Function Register PCON
In the NMOS version SAB 80515 the SFR PCON (address 87_H) contains only bit SMOD; in the
CMOS version SAB 80C515 there are more bits used (see table 4).
The bits PDE, PDS and IDLE, IDLS select the power-down mode or the idle mode, respectively,
when the use of the power saving modes is enabled by pin PE (see next page).
Semiconductor Group
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