SAB80515 Datasheet, PDF (55/270 Pages) Siemens Semiconductor Group – 8-Bit Single-Chip Microcontroller Family

On-Chip Peripheral Components
SEND enables the output of the shift register to the alternate output function line P3.0, and also
enables SHIFT CLOCK to the alternate output function line P3.1. SHIFT CLOCK is low during S3,
S4, and S5 of every machine cycle, and high during S6, S1, and S2, while the interface is
transmitting. Before and after transmission SHIFT CLOCK remains high. At S6P2 of every machine
cycle in which SEND is active, the contents of the transmit shift register is shifted one position to
the right.
As data bits shift to the right, zeros come in from the left. When the MSB of the data byte is at the
output position of the shift register, then the 1 that was initially loaded into the 9th position, is just
left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX control
block to do one last shift and then deactivates SEND and sets TI. Both of these actions occur at
S1P1 in the 10th machine cycle after "write-to-SBUF".
Reception is initiated by the condition REN = 1 and RI = 0. At S6P2 in the next machine cycle, the
RX control unit writes the bits 1111 1110 to the receive shift register, and in the next clock phase
activates RECEIVE.
RECEIVE enables SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK
makes transitions at S3P1 and S6P1 in every machine cycle. At S6P2 of every machine cycle in
which RECEIVE is active, the contents of the receive shift register are shifted one position to the
left. The value that comes in from the right is the value that was sampled at the P3.0 pin at S5P2 in
the same machine cycle.
As data bits come in from the right, 1 s shift out to the left. When the 0 that was initially loaded into
the rightmost position arrives at the leftmost position in the shift register, it flags the RX control block
to do one last shift and load SBUF. At S1P1 in the 10th machine cycle after the write to SCON that
cleared RI, RECEIVE is cleared and RI is set.
7.2.4.2 Mode 1, 8-Bit UART
Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB
first), and a stop bit (1). On reception through RxD, the stop bit goes into RB8 (SCON).
The baud rate for serial interface 0 is determined by the timer 1 overflow rate or by the internal baud
rate generator.
Figures 7-17 a) and b) show a simplified functional diagram of the serial channel in mode 1. The
generation of the baud rate clock is described in section 7.2.3.
Semiconductor Group
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