SAB80515 Datasheet, PDF (39/270 Pages) Siemens Semiconductor Group – 8-Bit Single-Chip Microcontroller Family

On-Chip Peripheral Components
7.1.1.2 MYMOS Port Driver Circuitry
The output driver circuitry of the MYMOS version (figure 7-3) consists of two pullup FETs (pullup
arrangements) and one pulldown FET:
– The transistor n1 is a very strong pullup transistor which is only activated for two oscillator
periods, if a 0-to-1 transition is executed by this port bit. Transistor n1 is capable of driving
high currents.
– The transistor n2 is a weak pullup transistor, which is always switched on. When the pin is
pulled down (e.g. when the port is used as input), it sources a low current. This value can be
found as the parameter I_IL in the DC characteristics.
– The transistor n3 is a very strong pull-down transistor which is switched on when a "0" is
programmed to the corresponding port latch. Transistor n3 is capable of sinking high currents
(I_OL in the DC characteristics).
A short circuit to V_CC must be avoided if the transistor is turned on because the high current
might destroy the FET.
7.1.1.3 ACMOS Port Driver Circuitry
The output driver circuitry of the ACMOS version (figure 7-3) is realized by three pullup FETs
(pullup arrangement) and one pulldown FET:
– The pulldown FET n1 is of n-channel type. lt is a very strong driver transistor which is capable
of sinking high currents (I_OL); it is only activated if a "0" is programmed to the port pin. A short
circuit to V_CC must be avoided if the transistor is turned on, since the high current might destroy
the FET.
– The pullup FET p1 is of p-channel type. lt is activated for two oscillator periods (S1P1 and
S1P2) if a 0-to-1 transition is programmed to the port pin, i.e. a "1" is programmed to the port
latch which contained a "0". The extra pullup can drive a similar current as the pulldown
FET n1. This provides a fast transition of the logic levels at the pin.
– The pullup FET p2 is of p-channel type. lt is always activated when a "1" is in the port latch,
thus providing the logic high output level. This pullup FET sources a much lower current than
p1; therefore the pin may also be tied to ground, e.g. when used as input with logic low input
level.
– The pullup FET p3 is of p-channel type. lt is only activated if the voltage at the port pin is
higher than approximately 1.0 to 1.5 V. This provides an additional pullup current if a logic high
level is to be output at the pin (and the voltage is not forced lower than approximately 1.0 to
1.5 V). However, this transistor is turned off if the pin is driven to a logic low level, e.g. when
used as input. In this configuration only the weak pullup FET p2 is active, which sources the
current I_IL. lf, in addition, the pullup FET p3 is activated, a higher current can be sourced (I_TL).
Thus, an additional power consumption can be avoided if port pins are used as inputs with a
low level applied. However, the driving cabability is stronger if a logic high level is output.
The described activating and deactivating of the four different transistors translates into four states
the pins can be:
– input low state (IL), p2 active only
– input high state (IH) = steady output high state (SOH) p2 and p3 active
– forced output high state (FOH), p1, p2 and p3 active
– output low state (OL), n1 active
Semiconductor Group
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