SAB80515 Datasheet, PDF (121/270 Pages) Siemens Semiconductor Group – 8-Bit Single-Chip Microcontroller Family

Interrupt System
lf two or more requests of different priority levels are received simultaneously, the request of the
highest priority is serviced first. lf requests of the same priority level are received simultaneously,
an internal polling sequence determines which request is to be serviced first. Thus, within each
priority level there is a second priority structure determined by the polling sequence, as follows (see
figure 8-8):
– Within one pair the "left" interrupt is serviced first
– The pairs are serviced from top to bottom of the table.
Figure 8-7
Special Function Registers IP0 and IP1 (Address 0A9H and 0B9H)
0A9H
0B9H
– WDTS IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0 IP0
–
– IP1.5 IP1.4 IP1.3 IP1.2 IP1.1 IP1.0 IP1
These bits are not used for interrupt control.
Corresponding bit locations in both registers are used to set the interrupt priority level of an interrupt
pair.
IP1.x
0
0
1
1
Bit
Function
IP0.x –
0 Set priority level 0 (lowest)
1 Set priority level 1
0 Set priority level 2
1 Set priority level 3 (highest)
Bit
IP1.0/IP0.0
IP1.1/IP0.1
IP1.2/IP0.2
IP1.3/IP0.3
IP1.4/IP0.4
IP1.5/IP0.5
Function
IE0/IADC
TF0/IEX2
IE1/IEX3
TF1/IEX4
RI + TI/IEX5
TF2 + EXF2/IEX6
Semiconductor Group
121