SAB80515 Datasheet, PDF (88/270 Pages) Siemens Semiconductor Group – 8-Bit Single-Chip Microcontroller Family

On-Chip Peripheral Components
7.5.2 Compare Function of Registers CRC, CC1 to CC3
The compare function of a timer/register combination can be described as follows. The 16-bit value
stored in a compare/capture register is compared with the contents of the timer register. lf the count
value in the timer register matches the stored value, an appropriate output signal is generated at a
corresponding port pin, and an interrupt is requested.
The contents of a compare register can be regarded as ’time stamp’ at which a dedicated output
reacts in a predefined way (either with a positive or negative transition). Variation of this ’time stamp’
somehow changes the wave of a rectangular output signal at a port pin. This may - as a variation
of the duty cycle of a periodic signal - be used for pulse width modulation as well as for a continually
controlled generation of any kind of square wave forms. In the case of the SAB 80(C)515, two
compare modes are implemented to cover a wide range of possible applications.
The compare modes 0 and 1 are selected by bit T2CM in special function register T2CON (see
figure 7-34). In both compare modes, the new value arrives at the port pin 1 within the same
machine cycle in which the internal compare signal is activated.
The four registers CRC, CC1 to CC3 are multifunctional as they additionally provide a capture,
compare or reload capability (the CRC register only, see section 7.5.1). A general selection of the
function is done in register CCEN (see figure 7-40). Please note that the compare interrupt CC0
can be programmed to be negative or positive transition activated. The internal compare signal (not
the output signal at the port pin!) is active as long as the timer 2 contents is equal to the one of the
appropriate compare registers, and it has a rising and a falling edge. Thus, when using the CRC
register, it can be selected whether an interrupt should be caused when the compare signal goes
active or inactive, depending on bit I3FR in T2CON. For the CC registers 1 to 3 an interrupt is
always requested when the compare signal goes active (see figure 7-36).
7.5.2.1 Compare Mode 0
In mode 0, upon matching the timer and compare register contents, the output signal changes from
low to high. lt goes back to a low level on timer overflow. As long as compare mode 0 is enabled,
the appropriate output pin is controlled by the timer circuit only, and not by the user. Writing to the
port will have no effect. Figure 7-35 shows a functional diagram of a port latch in compare mode 0.
The port latch is directly controlled by the two signals timer overflow and compare. The input line
from the internal bus and the write-to-latch line are disconnected when compare mode 0 is enabled.
Compare mode 0 is ideal for generating pulse width modulated output signals, which in turn can be
used for digital-to-analog conversion via a filter network or by the controlled device itself (e.g. the
inductance of a DC or AC motor). Mode 0 may also be used for providing output clocks with initially
defined period and duty cycle. This is the mode which needs the least CPU time. Once set up, the
output goes on oscillating without any CPU intervention. Figure 7-36 and 7-37 illustrate the function
of compare mode 0.
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