LC890561W Datasheet, PDF (44/47 Pages) Sanyo Semicon Device – CMOS IC Digital Audio Interface Receiver with Built-in Data Buffer Memory

LC890561W
14.6.2 Read Out Register 0xE9 (First 48bit channel status data)
• For reading the register, set the CCB address as 0xE9.
• CSFLAG (DO0), ERROR (DO1), FSB0 (DO2), FSB1 (DO3), F0 (DO4), F1 (DO5) and F2 (DO6) output the status of
pin 25 (CSFLAG), pin34 (ERROR), pin26 (F0/FSB0), pin27 (F1/FSB1) and pin28 (F2) at the time of read.
• The channel status bits 0 to 47 are output with LSB first.
• The channel status data after a CCB address setup is not updated.
• The latest data can be transferred by reading the falling edge of CSFLAG as the load enable signal.
• The relation between the read register and channel status data is shown below.
Table 14.4 Read register for the first 48bits of channel status data
Register
Bit No.
Contents
Register
Bit No.
Contents
DO8
Bit 0
Application
DO32
Bit 24
Sampling
DO9
Bit 1
Control
DO33
Bit 25
frequency
DO10
Bit 2
DO34
Bit 26
DO11
Bit 3
DO35
Bit 27
DO12
Bit 4
DO36
Bit 28
Clock accuracy
DO13
Bit 5
DO37
Bit 29
DO14
Bit 6
Not defined
DO38
Bit 30
Not defined
DO15
Bit 7
DO39
Bit 31
DO16
Bit 8
Category code
DO40
Bit 32
Word length
DO17
Bit 9
DO41
Bit 33
DO18
Bit 10
DO42
Bit 34
DO19
Bit 11
DO43
Bit 35
DO20
Bit 12
DO44
Bit 36
Not defined
DO21
Bit 13
DO45
Bit 37
DO22
Bit 14
DO46
Bit 38
DO23
Bit 15
DO47
Bit 39
DO24
Bit 16
Source number
DO48
Bit 40
DO25
Bit 17
DO49
Bit 41
DO26
Bit 18
DO50
Bit 42
DO27
Bit 19
DO51
Bit 43
DO28
Bit 20
Channel number
DO52
Bit 44
DO29
Bit 21
DO53
Bit 45
DO30
Bit 22
DO54
Bit 46
DO31
Bit 23
DO55
Bit 47
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