LC890561W Datasheet, PDF (38/47 Pages) Sanyo Semicon Device – CMOS IC Digital Audio Interface Receiver with Built-in Data Buffer Memory

DLPO
DOM[1:0]
EWT[1:0]
LC890561W
DLMP output polarity setting (Enable, when FSEL = 1)
0 : Normal L output (default)
1 : Normal H output
DATAO, DATAO2 mute setting
00 : The data chosen by SMOD is outputted (default)
01 : Only DATAO is muted
10 : Only DATAO2 is muted
11 : DATAO and DATAO2 are muted
An ERROR output waiting time setup after a PLL lock
00 : Cancel error after preamble B is counted to 48 (default)
01 : Cancel error after preamble B is counted to 12
10 : Cancel error after preamble B is counted to 6
11 : Cancel error after preamble B is counted to 3
The pulse width of XSTATE output after a PLL lock by input data is as follows.
XSTATE pulse width = {192/fs × (“EWT[1:0] count value” - 2)}
Input fs
32kHz
44.1kHz
48kHz
88.2kHz
96kHz
176.4kHz
192kHz
Table 14.3. Pulse Width of XSTATE output
EWT[1:0]
“00”
“01”
“10”
276.0ms
60.0ms
24.0ms
200.2ms
43.5ms
17.4ms
184.0ms
40.0ms
16.0ms
100.1ms
21.7ms
8.7ms
92.0ms
20.0ms
8.0ms
50.0ms
10.8ms
4.3ms
46.0ms
10.0ms
4.0ms
“11”
6.0ms
4.3ms
4.0ms
2.1ms
2.0ms
1.0ms
1.0ms
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