LC890561W Datasheet, PDF (16/47 Pages) Sanyo Semicon Device – CMOS IC Digital Audio Interface Receiver with Built-in Data Buffer Memory

LC890561W
12.5 Serial Audio Data Input and Output
12.5.1 Output Data Format (DATAO, DATAO2, DOSEL0, DOSEL1)
• DATAO and DATO2 output the digital data after demodulation. DATAO2 should be switched by the VSEL
command since DATAO2 is sharing pin with validity flag output.
• The output data format is set with DOSEL0 and DOSEL1 terminals, or the DOSW command. The output data is 24bit
I²S output when setup is DOSW=1. The setup of DOSW is given priority over DOSEL0 and DOSEL1.
DOSEL1 pin
0
0
1
1
Table 12.5 Data output format Selection (DOSW = 0)
DOSEL0 pin
DATAO and DATAO2 pin
0
(0) 24bit MSB-first left justified
1
(1) 24bit MSB-first right justified
0
(2) 20bit MSB-first right justified
1
(3) 16bit MSB-first right justified
• Data is output in synchronization with the falling edge of BCK from the edge of LRCK immediately after the ERROR
flag goes low. However, this is the case that the delay setup is disabled (initial setting). When the delay setup is
effective, DATAO is output after the delay time set. The delay setting is not applicable to DATA02. For information
about these settings, see section “13. Output Data Delay Function”.
LRCK (O)
BCK (O)
DATAO (O)
DATAO2 (O)
L-ch
R-ch
MSB
LSB
Max. 24bit
MSB
LSB
Max. 24bit
(0): Setting with DOSEL0, DOSEL1
MSB
LRCK (O)
BCK (O)
DATAO (O)
LSB
DATAO2 (O)
L-ch
R-ch
MSB
LSB
16, 20, 24bit
MSB
LSB
16, 20, 24bit
(1) (2) (3): Setting with DOSEL0, DOSEL1
LRCK (O)
BCK (O)
DATAO (O)
DATAO2 (O)
R-ch
L-ch
MSB
LSB
24bit
MSB
LSB
24bit
(4): Setting with the DOSW command
Figure 12.2 Data Output Timing Charts
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