LC890561W Datasheet, PDF (20/47 Pages) Sanyo Semicon Device – CMOS IC Digital Audio Interface Receiver with Built-in Data Buffer Memory

LC890561W
12.7 Output Data Error Processing
12.7.1 Upon Error Occurrence (Lock Error and Parity Error)
• The data processing upon error occurrence is described below. If input parity errors occur eight times or more in
succession, transfer data is replaced by the data held in L-ch and R-ch of the previous frame in the case of PCM audio
data. However, if the data is Non-PCM burst data, error data is output without change as the transfer data. Non-PCM
burst data is detected based on data detected prior to occurrence of an input parity error when channel status bit 1 goes
high or when burst preamble Pa and Pb are detected.
• For the channel status, the data of the previous block is held in bit when a parity error occurs, regardless of the data type.
• Output data is muted upon occurrence of a PLL lock error or nine continuous parity errors.
Table 12.6 Data Processing Upon Error Occurrence
Data
PLL lock error
Input parity error (a)
Input parity error (b)
DATAO and DATAO2
L
L
Previous value data
F0, F1, F2 outputs
L
Output
Output
Channel status
L
Previous value data
Previous value data
Validity flag
L
Output
Output
* Input parity error (a): If occurred 9 times or more in succession
* Input parity error (b): If occurred 8 times or fewer, in the case of PCM audio data
* Input parity error (c): If occurred 8 times or fewer, in the case of Non-PCM burst data
Input parity error (c)
Output
Output
Previous value data
Output
• Figure 12.7 shows an example of data processing upon occurrence of a parity error
Input data
1 occurrence
L-1 R-1 L-2 R-2 L-3 R-3 L-4 R-4 L-5 R-5 L-6 R-6 L-7 R-7 L-8 R-8
ERROR
LRCK
DATAO
L-0 R-0 L-1 R-0 L-2 R-2 L-2 R-2 L-2 R-2 L-2 R-2 L-2
R-ch
L-ch R-ch
…
Previous value data Previous value data
9 times or more: Muting
Figure 12.7 Example of Data Processing Upon Parity Error Occurrence (non delay setting)
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