LC890561W Datasheet, PDF (31/47 Pages) Sanyo Semicon Device – CMOS IC Digital Audio Interface Receiver with Built-in Data Buffer Memory

LC890561W
13.4 Monitor Setup for Output Data Delay Setting (FSEL)
• Information available for delay setting of output data can be monitored by FSB0, FSB1 and DLMP pins by switching
the FSEL command. This setup is switched by FSEL command.
• FSB0 and FSB1 terminal classifies the calculation result of the sampling frequency of input data into standard
frequency, standard ×2, and standard ×4 and outputs.
• However, when S/PDIF data is not received, PLL is not locked, or when the mode 4 is set up with MODE0 and
MODE1 terminal, FSB0 and FSB1 terminals output low.
• DLMP terminal outputs a pulse signal during the waiting time period at the time of ERROR flag switching, or during
the mute period at the time of a delay setup. This pulse can change polarity by DLPO command.
FSB1 pin
L
L
H
H
Table 13.3. FSB0 and FSB1 output state (FSEL = 1)
FSB0 pin
Output state
S/PDIF data is not received, or PLL is unlocked, when the mode 4 is set up with
L
MODE0 and MODE1 terminal.
S/PDIF data is either of the 32kHz or 44.1kHz or 48kHz.
H
(Standard frequency)
S/PDIF data is either of the 88.2kHz or 96kHz.
L
(Standard ×2 frequency)
S/PDIF data is either of the 176.4kHz or 192kHz.
H
(Standard ×4 frequency)
ERROR
XSTATE
(XSTP = 0)
DLMA to B
State
DLMX, Y
State
DATAO2 _Recovery
Delay setting of recovery data
Delay setting of SDIN
SDIN
Recovery
DATAO _Recovery
DLMP
(DLPO = 0)
Delay time
SDIN
SDIN
Recovery
Delay time
Recovery
Mute
Mute = Delay time
Mute
Mute = Delay time
Figure 13.10 Timing Chart for DLMP Output Mute Period (command cancel is not included)
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