LC890561W Datasheet, PDF (21/47 Pages) Sanyo Semicon Device – CMOS IC Digital Audio Interface Receiver with Built-in Data Buffer Memory

LC890561W
12.7.2 Upon Error Recovery (Lock)
• When preamble B, M and W are detected, PLL is locked and data demodulation begins.
• DATAO and DATAO2 output data are output from the L/R clock edge after ERROR goes low.
• The start timing of the ERROR flag, and the DATAO and DATAO2 output data are shown in Figure 12.8.
• The above operation is in case the delay setup is not done. For information on operations with delay settings, see
section “13. Output Data Delay Function”.
ERROR
Internal lock signal
3ms to 300ms
OK
LRCK
DATAO
Data
Output start from LRCK edge immediately after ERROR flag is lowered
Figure 12.8 Data Processing at Data Demodulation Start (non delay setting)
12.8 Channel Status Emphasis Information Output (EMPHA)
• EMPHA outputs channel status information that indicates the presence or absence of 50/15µsec pre-emphasis.
• EMPHA is output immediately after the detection of ERROR even during high output.
EMPHA pin
L
H
Table 12.7 EMPHA Output
Output condition
No pre-emphasis
50/15µs pre-emphasis
12.9 Channel Status Bit 1 Output (AUDIO)
• AUDIO outputs bit 1 of the channel status that indicates whether transfer data has PCM audio data or data other than
audio.
• AUDIO is output immediately after the detection of ERROR even during high output.
AUDIO pin
L
H
Table 12.8 AUDIO Output
Output condition
PCM audio data (CS bit 1 = L)
Data other than audio (CS bit 1 = H)
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