LC890561W Datasheet, PDF (26/47 Pages) Sanyo Semicon Device – CMOS IC Digital Audio Interface Receiver with Built-in Data Buffer Memory

LC890561W
13.2 DATAO Output Data Processing
• When any of the DTMA [4:0], DTMB [3:0], DTMC [2:0], DTMX [4:0], DTMY [3:0] is set up (setup of those other
than an initial state), delay processing of output data is performed.
• Delay processing of the target data and mute processing of output data are explained below.
13.2.1 Output Data Delay Setup after Recovery Processing (Setting at the state of ERROR = H)
• When the DTMA[4:0], DTMB[3:0] and DTMC[2:0] commands are set up or changed during high output of ERROR
flag, data is written into memory in synchronization with the rising edge of XSTATE after PLL is locked.
• Readout of the data written in the memory is started after the set delay time (frame).
• The data read out is constantly output form DATAO with the delay of the setup time.
• DATAO will be muted until the set delay time is over, because sufficient data is not written into memory immediately
after the low output of ERROR flag.
DIN*
Lock state
ERROR
XSTATE
(XSTP = 0)
DATAO2
DATAO
Wn-2 Mn-1 Wn-1
Unlock
M1 W1 M2 W2 M3
Lock
Mn+1 Wn+1 Mn+2 Wn+2
Same
SDIN data
SDIN data
0 data (mute) L0 R0
Ln Rn Ln+1 Rn+1
0 data (mute)
L0 R0
Wait period:
3ms to 300ms
Delay time
Figure 13.1 Timing Chart for Output Data after Setup or Change of the Delay Time During PLL Lock-in
• When the DTMA[4:0], DTMB[3:0] and DTMC[2:0] commands are canceled during high output of ERROR flag, data
is output from DATAO synchronizing with the rising edge of XSTATE after PLL is locked. This is normal operation
which does not perform a delay processing setup.
DIN*
Lock state
ERROR
XSTATE
(XSTP = 0)
DATAO2
DATAO
Wn-2 Mn-1 Wn-1
Unlock
M1 W1 M2 W2 M3
Lock
Same
SDIN data
SDIN data
0 data (mute) L0 R0
0 data (mute) L0 R0
Wait period:
3ms to 300ms
Mn+1 Wn+1 Mn+2 Wn+2
Ln Rn Ln+1 Rn+1
Ln Rn Ln+1 Rn+1
Figure 13.2 Timing Chart for Output Data after Cancel of the Delay Time Setting During PLL Lock-in
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