LC890561W Datasheet, PDF (30/47 Pages) Sanyo Semicon Device – CMOS IC Digital Audio Interface Receiver with Built-in Data Buffer Memory

LC890561W
13.3 Time Lag of the Command Setup (DTMA[4:0], DTMB[3:0], DTMC[2:0], DTMX[4:0], DTMY[3:0])
• DTMA [4:0], DTMB [3:0], DTMC [2:0], DTMX [4:0] and DTMY [3:0] commands are performed synchronizing with
the rising edge (the falling edge is used for the I²S data format setup) of LRCK clock. Therefore, the time lag of 1
LRCK cycle at the maximum arises after setting up the command until it is executed.
• Moreover, the minimum interval of a command setup becomes 1 LRCK period.
• Furthermore, data processing by command setup is performed after 1 LRCK period progress.
• Setup, change and cancel of the delay time are processed per command.
• Setup, change and cancel of the command in the same address are performed for the data of the target input sampling
frequency.
• Cancel of the command is the case where the delay time is set as 0.
CE
CL
DI
State of
Commands
B0 B1
LRCK
Set-up of
Commands
DATAO
A2 A3 DI0 DI1 DI2
ex.) Delay = 90ms
DI12 DI13 DI14 DI15
Microcontroller
interface
ex.) Delay = 40ms
Change point
Delay = 90ms
Delay = 40ms
Before (90ms)
Time lag of command setting
Time lag of data output
After (40ms)
Figure 13.9 Timing Chart from a Command Setup to Execution
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