LC890561W Datasheet, PDF (10/47 Pages) Sanyo Semicon Device – CMOS IC Digital Audio Interface Receiver with Built-in Data Buffer Memory

LC890561W
7. System Reset (XMODE)
• The system operates normally when XMODE pin is set to high level after 3.0V or higher supply voltage is applied.
• After power-on, the system is reset by setting XMODE to low again.
• Make sure to reset the system after turning on the power.
DVDD
XMODE
3.0V
t
t > 200µ
Reset state
System operation
Figure 7.1 Reset Timing Chart
8. PLL (LPF)
• It has a build-in VCO (Voltage Controlled Oscillator) and synchronizes with sampling frequencies of 32kHz,
44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz and 192kHz.
• The lock judgment of PLL is performed by detection of preamble B, M and W.
• The lock frequency of PLL is selected by CKSEL0 and CKSEL1. However, only 256fs is selectable on the system
which input sampling frequency is over 96kHz. The proper PLL function to input over 96kHz will not be ensured
when other frequency value is selected.
• LPF is pin for loop filter of PLL and connects resistor and capacitor as shown below.
LPF
R0
220Ω
C0
0.1µF
C1
0.068µF
R0
C1
C0
Figure 8.1 Configuration of a Loop filter
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