LC890561W Datasheet, PDF (1/47 Pages) Sanyo Semicon Device – CMOS IC Digital Audio Interface Receiver with Built-in Data Buffer Memory

Ordering number : EN*8226
CMOS IC
LC890561W ^{Digital Audio Interface Receiver}
with Built-in Data Buffer Memory
Overview
The LC890561W is an audio LSI that synchronizes with the input signal and demodulates the signal into the normal
format signal during data transmission between digital audio devices via the IEC60958 and EIAJ CP-1201.
It supports sampling frequencies of up to 192kHz. It is replaceable with the existing LC89056W by devising the
mounting board. The LC890561W has a build-in data buffer memory that allows a lip synchronization function.
It allows the audio data output to be delayed after demodulation.
The LC890561W is applicable to the reception of digital data transmission, such as AV amplifier, AV receiver and car
audio.
1. Features
• Built-in PLL circuit to synchronize with transferred input bi-phase signal.
• Built-in PLL error lock prevention circuit for accurate locking.
• Equipped with three S/PDIF data input pins that support TTL input port of 5V interface.
• Receives sampling frequencies of 32kHz to 192kHz.
• Outputs the following clocks: 512fs, 384fs, 256fs, 64fs and fs.
• Outputs the fs information of 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz 176.4kHz and 192kHz.
• Built-in oscillation amplifier: 24.57MHz or 12.28MHz
• Outputs transitional period signal where VCO clock and oscillation amplifier clock are switched.
• Outputs up to 24bits of data. Also supports 24bit I²S data.
• Built-in SRAM of 24576word × 24bit to allow delay of output data.
• Two types of data output pins to set delay or not delay of output data.
• Contains the pin that outputs the delay setting state of output data.
• Contains the output pin for bit 1 (Non-PCM data detection bit) of channel status.
• Outputs channel status emphasis information.
• Outputs update flag for first 48bits of channel status.
• Outputs synchronization signal for burst preambles Pa, Pb, Pc and Pd.
• Outputs validity flag.
• Switching of the serial audio input data and recovery data is possible.
• The delay setting of output data for serial audio data input is possible.
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at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
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products described or contained herein.
92706 / D0205 MS IM No.8226-1/47