LC890561W Datasheet, PDF (22/47 Pages) Sanyo Semicon Device – CMOS IC Digital Audio Interface Receiver with Built-in Data Buffer Memory

LC890561W
12.10 First 48 Channel Status Bits Update Flag Output (CSFLAG)
• CSFLAG compares the first 48 bits of channel status data of the previous block with those of the current block and
outputs low in case they are the same, and high in case they are different, for 1 block of 192 frames. Therefore the
channel status data output after the falling edge of the CSFLAG is the latest data.
• CSFLAG outputs high regardless of the comparison result until ERROR outputs low. After ERROR output becomes
low, CSFLAG outputs low after the first 48bit data of the previous data and the current data have been confirmed to
be identical.
CSFLAG pin
L
H
Table 12.9 CSFLAG Output
Output condition
Previous data current data are identical
Previous data differs from current data
bit 191 bit 191 bit 0
bit 0
Input data ^{M191 W191 B}
W
LRCK
CSFLAG
bit 46
W46
bit 47
M47
bit 47
W47
bit 48
M48
bit 48
W48
bit 49
M49
bit 49
W49
bit 50
M50
Become “H” when not identical to previous block
Figure 12.9 Timing Chart for Channel Status Update Flag Output
12.11 Non-PCM Burst Preamble Detection Signal Output (BPSYNC)
• BPSYNC outputs low while Non-PCM burst preamble Pa, Pb, Pc and Pd output, when Pa and Pb are detected
following continuous all zero data of two frame. However, when output data delay is set up, low period of a BPSYNC
signal and the output period of the Non-PCM burst preamble Pa, Pb, Pc, and Pd do not match. In this case, BPSYNC
is output ahead of Pa, Pb, Pc, and Pd data.
• Pa, Pb, Pc and Pd are detected from the receive data even when an input parity error occurs.
Input data
Preamble
Burst payload
000h 000h 000h 000h Pa Pb Pc Pd 2
2
3
3
4
4
LRCK
DATAO
000h 000h 000h 000h Pa Pb Pc Pd 2
2
BPSYNC
Figure 12.10 Timing Chart for Pa, Pb, Pc and Pd Detection Signal Output
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