LC890561W Datasheet, PDF (36/47 Pages) Sanyo Semicon Device – CMOS IC Digital Audio Interface Receiver with Built-in Data Buffer Memory

DIS[1:0]
FSL[1:0]
ERF[1:0]
BMOD
CKDV
LC890561W
S/PDIF Input data pin setting
00 : Follow DISEL setting (default)
01 : Select DIN0
10 : Select DIN1
11 : Select DIN2
S/PDIF Input data reception range setting
00 : Normal mode (Same as the mode 1 of MODE0 and MODE1)
(default)
01 : 32kHz to 48kHz
10 : Fs free mode A (Same as the mode 2 of MODE0 and MODE1)
11 : 32kHz to 96kHz
If set reception range is exceeded, ERROR is output as high even if PLL is locked.
Parity error flag output setting if 8 or fewer input parity errors occur in succession
00 : Error flag is not output (default)
01 : Only output during sub-frame with error
10 : Reserved
11 : Only output upon Non-PCM burst data recognition
In case ERF[1:0]=00, although no error flag is output, the process for error is executed for
output data.
In case ERF[1:0]=01, no error flag is output when the delay setting of output data is
performed.
In case ERF[1:0]=11, Non-PCM burst data recognition is performed when channel status
bit1 is high.
DOUT output state setting
0 : Outputs a selected input data (default)
1 : L fixed
CKOUT output state setting when PLL is locked
0 : Output CKSEL0 and CKSEL1 setting clock (default)
1 : Output 1/2 of CKSEL0 and CKSEL1 setting clock
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