LC890561W Datasheet, PDF (28/47 Pages) Sanyo Semicon Device – CMOS IC Digital Audio Interface Receiver with Built-in Data Buffer Memory

LC890561W
13.2.3 Output Data Delay Setup of SDIN Input Data (Setting at the state of ERROR = L)
• When the DTMX[4:0] or DTMY[3:0] commands are set up during low output of ERROR flag, data is written to a
memory in synchronization with the rising edge of XSTATE after PLL unlock.
• Readout of the data written in the memory is started after the set delay time (frame).
• The data read out is constantly output form DATAO with the delay of the setup time.
• DATAO will be muted until the set delay time is over, because sufficient data is not written into memory immediately
after the low output of ERROR flag.
DIN* _{Mm-1 Wm-1 Mm Wm}
SDIN _{Ln-2 Rn-1 Ln-1 Rn Ln}
Lock state
Lock
ERROR
XSTATE
(XSTP = 0)
DATAO2
Recovery data
L1 R1 L2 R2 L3
Unlock
Lo Ro Lo+1 Ro+1
0 data (mute) L0 R0
Ro-2 Lo-1 Ro-1 Lo
DATAO
Recovery data
0 data (mute)
L0 R0 L1
Wait period:
5ms to 12ms
Delay time
Figure 13.5 Timing Chart for Output Data after Setup or Change of the Delay Time During PLL Unlock
• When the DTMX[4:0] or DTMY[3:0] commands are canceled during low output of ERROR flag, data is output from
DATAO synchronizing with the rising edge of XSTATE after PLL unlock. This is normal operation which does not
perform a delay processing setup.
DIN* _{Mm-1 Wm-1 Mm Wm}
SDIN _{Ln-2 Rn-1 Ln-1 Rn Ln}
Lock state
Lock
ERROR
XSTATE
(XSTP = 0)
DATAO2
Recovery data
L1 R1 L2 R2 L3
Unlock
Lo Ro Lo+1 Ro+1
0 data (mute) L0 R0
Ro-2 Lo-1 Ro-1 Lo
DATAO
Recovery data
0 data (mute) L0 R0
Ro-2 Lo-1 Ro-1 Lo
Wait period:
5ms to 12ms
Figure 13.6 Timing Chart for Output Data after Cancel of the Delay Time Setting During PLL Unlock
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