LC890561W Datasheet, PDF (12/47 Pages) Sanyo Semicon Device – CMOS IC Digital Audio Interface Receiver with Built-in Data Buffer Memory

LC890561W
11. Setting of MODE0 and MODE1
• Selected operation mode with MODE0 and MODE1 terminals.
Mode No.
1
2
3
4
Table 11.1 Setting operating mode
MODE1 pin
MODE0 pin
Function
0
0
Normal mode
0
1
Fs free mode A
1
0
Test mode
1
1
Fs free mode B
(a) Mode1: Normal mode
−Input data fs of 32kHz to 192kHz is received only when CKOUT=256fs.
−The proper reception of data over 96kHz will not be ensured when other than 256fs is used for CKOUT output
setting.
(b) Mode2: Input fs free mode A (Terminal setting priority)
−Restriction of input fs is canceled.
−12.288MHz or 24.576MHz clock is supplied to XIN.
−The receiving range of input data is based on a setup of CKOUT output.
−Fs calculation of input data is performed in the possible range. (fs ± 3 to 4%)
(c) Mode3: Test mode
−Do not set this mode for the test.
(d) Mode4: Input fs free mode B (Terminal setting priority)
−Restriction of input fs is canceled.
−12MHz to 25MHz arbitrary clock is supplied to XIN.
−The reception range of input data is based on a setup of the CKOUT output.
−Input fs is not calculated. In this case, all F0, F1 and F2 output low.
−Output data delay after recovery processing cannot be set. However, the delay setting of the SDIN input data is
possible.
• In the normal mode, when fs of input data is out of the reception setting range or the fs calculation range (≠target fs
frequency ± 3 to 4%), ERROR is output high even if PLL is locked.
• In the input fs free mode, the reception range is set up without any restriction and fs calculation result is set so that it
is not reflected in ERROR output. ERROR output will be set to low if PLL is locked.
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