LC890561W Datasheet, PDF (14/47 Pages) Sanyo Semicon Device – CMOS IC Digital Audio Interface Receiver with Built-in Data Buffer Memory

LC890561W
• The frequency required for XIN and XOUT is selected with XSEL. Normally the crystal resonator clock set here or
external clock must be input. Moreover, make sure to connect a transducer to XIN and XOUT or supply a clock to
XIN. (Normal input)
• In the case of setting the input fs free mode B, 12MHz to 25MHz arbitrary clock must be supplied to between XIN
and XOUT. This case, XSEL must select the closer frequency of transducer to be connected.
Table 12.2 XIN Supply Frequency Selection
XSEL pin
Frequency
0
24.576MHz
1
12.288MHz
• XIN and XOUT are valid when PLL is unlocked, and oscillation amplifier clock or the divided clock of external input
clock is output from the clock output pins.
• When the PLL is locked the oscillation amplifier is stopped so that it does not influence the VCO clock. The clock
supplied to XIN is blocked in I/O block and the inside operates only with VCO clock. However, XIN and XOUT can
also always be operated with the XCNT command. In this case, the XIN and XOUT clock is at risk of influencing the
VCO clock.
• XMCK outputs the clock generated with oscillation amplifier of XIN and XOUT as a clock for A/D converter. The
XMCK clock frequency is selected with the XADC command.
• When oscillation amplifier is set up for continues operation, XMCK can be stopped only during PLL is locked. It is
set by the XCKS command. XCKS is for reducing clock interference to input and output buffer during the continuous
operation of oscillation amplifier.
• Table 12.3 shows the status of the XIN, XOUT and XMCK pins when PLL is locked and unlocked.
Table 12.3 Status of Oscillation Amplifier Circuit when PLL Locked or Unlocked (XCNT = 0)
Pin name
Specified time after locked *
Unlocked status
XIN
Input disabled
Input enabled
XOUT
H
XIN inverted clock output
XMCK
L
1/1 or 1/2 XIN clock output
* Note: The specified time is the time from when PLL is locked until 8 preamble B is counted to eight.
During this time, the input sampling frequency is calculated.
• XSTATE outputs low from the time PLL is locked until the ERROR goes low (lock-in stage), or from the time PLL is
unlocked until the output clock is stabilized (unlock stage).
• L pulse width of XSTATE in lock-in process is a period from the PLL lock to the cancel of the ERROR. It is decided
from the count value of Preamble B and sampling frequency of input data. For the ERROR output waiting time, see
explanation of EWT[1:0] commands.
• L pulse width of XSTATE in unlock process is 512 count periods of fs clock which uses oscillation amplifier as a
source clock. For example, when an oscillation amplifier clock is 12.288MHz, fs clock output from LRCK is set to
48kHz. In other words, about 10ms that counted this fs 512 times is L pulse width period. In addition, the time until
the start of oscillator is required when the crystal oscillator is connected to oscillation amplifier. In this case, L pulse
width is added during start-up time.
• For the XMCK output timing, see Figure 12.1.
• XSTATE outputs the low pulse, when change arises on the clocks. (when XSTP=0 setup)
• Also, the output polarity of XSATAE can be changed by the XSTP command.
• All functions of a VCO oscillation clock and an oscillation amplifier can be stopped by the STOP command. At this
time, all output clock terminals serve as DC output.
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