LC890561W Datasheet, PDF (18/47 Pages) Sanyo Semicon Device – CMOS IC Digital Audio Interface Receiver with Built-in Data Buffer Memory

LC890561W
12.5.3 Output Data Changing (DATAO, DATAO2, SDIN)
• DATAO and DATAO2 output demodulation data when PLL is locked, and output SDIN input data when PLL is
unlocked. This switching is automatically performed according to the state of PLL lock or unlock.
• During the selection of SDIN input data, it must be switched to the clock source that is in synchronized with SDIN data.
• SDIIN input data is output to DATAO and DATAO2 with the SMOD command setting regardless of the lock /
unlock state of PLL. In the case of switching PLL in the lock state, clock source is also switched to XIN. Furthermore,
an ERROR flag also outputs high and a XSTATE signal also changes.
• DATAO and DATAO2 output can be muted forcibly with setting of the DOM[1:0] commands.
PLL state
XSTATE
(XSTP = 0)
ERROR
DATAO
DATAO2
UNLOCK
SDIN data
LOCK
Muted
(a): Lock-in stage
Demodulation data
PLL state
XSTATE
(XSTP = 0)
ERROR
DATAO
DATAO2
LOCK
UNLOCK
Demodulation data
Muted
(b): Unlock stage
SDIN data
Figure 12.4 DATAO and DATAO2 Outputs Data Chang Timing Charts
12.5.4 Data System Diagram (DIN0, DIN1, DIN2, SDIN, DOUT, DATAO, DATAO2)
• Data system diagram is shown below.
• The delay setup for DATAO is possible. However, the delay setup for DATAO2 is impossible because DATAO2
does not go through a memory.
• DIN0 to DIN2 and SDIN input data are output to DATAO and DATAO2 behind two frames. Delay setup of output
data is processed with the DATAO output with 2-frame delay against the input data as delay for 0ms.
• Since DATAO2 shares the pin with the validity flag output, it should be changed by the VSEL command. The initial
value of VSEL is the validity flag output.
SDIN
DIN0
DIN1
DIN2
Data register
MUX
(3in/1out)
DIR
VF
[SMOD]
Buffer
RAM
[VSEL]
Figure 12.5 Data System Diagram
DATAO
VF/DATAO2
DOUT
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