LC890561W Datasheet, PDF (13/47 Pages) Sanyo Semicon Device – CMOS IC Digital Audio Interface Receiver with Built-in Data Buffer Memory

LC890561W
12. Function
12.1 Input Data (DIN0, DIN1, DIN2, DOUT, DISEL)
• DIN0, DIN1 and DIN2 are input pins that support TTL level inputs (5V tolerance).
• DIN0, DIN1 and DIN2 are grounded with the pull-down resistor when they are not selected.
• The input pin is selected with DISEL and the DIS[1:0] commands. (Command setting priority)
• With DISEL, it is selected from DIN0 or DIN1. With DIS[1:0], it is selected from DIN0, DIN1 or DIN2.
• DOUT performs through output the bi-phase data input to the selected data input pin. When, however, DOUT is not
used, low fixed output setting is recommended in order to reduce the clock jitter.
Table 12.1 Data Input Pin Selection
DISEL pin
Input pin to be demodulated
0
DIN0
1
DIN1
12.2 Input Data Reception Range
• The input data reception range can be extended and restricted with FSL0 and FSL1 commands, and CKSEL0 and
CKSEL1 terminals. Also, the restriction can be canceled with MODE0 and MODE1.
• In the initial status at power ON, although sampling frequency of input data can be received up to 192kHz, sampling
frequency of input data to be received can be restricted up to 48kHz or 96kHz. In this case, input data over this range
results in an error and output data is muted.
• For information about these settings, see section “14. Microcontroller Interface”.
12.3 VCO and Oscillation Amplifier Clock (XIN, XOUT, XMCK, XSEL, XSTATE)
• The oscillation amplifier circuit is configured with XIN and XOUT. XIN accepts the input of the external clock.
• The clock generated with XIN and XOUT is used for the following purposes.
−Clock for detection of data input
−Clock for A/D converter in analog source mode
−Clock for calculation of input sampling frequency
−Clock for PLL error lock countermeasure
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