LC890561W Datasheet, PDF (37/47 Pages) Sanyo Semicon Device – CMOS IC Digital Audio Interface Receiver with Built-in Data Buffer Memory

LC890561W
CCB address: 0xEB
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
XCKS
XSTP
0
CKPO
VSEL
FSEL
0
IMOD
DI15
DI14
DI13
DI12
DI11
DI10
DI9
DI8
EWT1
EWT0
0
0
DOM1
DOM0
0
DLPO
IMOD
FSEL
VSEL
CKPO
XSTP
XCKS
CL pin setting
0 : Data readout is performed with normal L clock (default)
1 : Data readout is performed with normal H clock
F0/FSB0, F1/FSB1, F2/DLMP pin setting
0 : F0, F1, F2; Input sampling frequency calculated signal output
(default)
1 : FSB0, FSB1, DLMP; The monitor signal output for a delay setting
VF/DATAO2 pin setting
0 : VF; Validity flag output (default)
1 : DATAO2; Data output after demodulation
CKOUT output polarity setting
0 : Normal output (default)
1 : Inverted-phase output
XSTATE output polarity setting
0 : Normal H output (default)
1 : Normal L output
XMCK output setting while PLL is locked (Enable, when XCNT= 1)
0 : Output according to the operation of oscillation amplifier (default)
1 : Stop output only when PLL is locked during the continuous
operation of oscillation amplifier
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