LC890561W Datasheet, PDF (15/47 Pages) Sanyo Semicon Device – CMOS IC Digital Audio Interface Receiver with Built-in Data Buffer Memory

LC890561W
12.4 Output Clock (CKOUT, BCK, LRCK)
• The CKOUT output clock is selected by setting CKSEL0 and CKSEL1 terminals.
CKSEL1 pin
0
0
1
1
Table 12.4 CKOUT Output Clock Selection
CKSEL0 pin
0
1
0
1
CKOUT pin
256fs output
384fs output
512fs output
512fs/2 output
• 256fs must be chosen when receiving data over 96kHz as above table. There is no restriction of selection for data
reception under 96kHz.
• 512fs/2 set PLL band as 512fs, and CKOUT clock outputs one half (256fs output).
• 64fs clock (64fs only) is outputted from BCK, and the fs clock is outputted from LRCK.
• When PLL is unlocked, the XIN and XOUT oscillation amplifier clock or the external input clock is output from
CKOUT, and the divided clock of this clock is outputted from BCK and LRCK.
• Output of 1/2 CKOUT clock by CKDV command is possible.
• Reverse of the polarity of CKOUT clock by CKPO command is also possible.
• In the PLL lock and unlock phases, the CKOUT (BCK and LRCK likewise) clock switch timing is as follows.
DIN0 to DIN2
PLL lock state
XIN clock
VCO clock
XSTATE
(XSTP = 0)
ERROR
CKOUT
UNLOCK
Digital data
LOCK
1ms to 276ms
(a): During lock-in phase
Same
DIN0 to DIN2
PLL lock state
XIN clock
VCO clock
XSTATE
(XSTP = 0)
ERROR
CKOUT
Digital data
LOCK
UNLOCK
Same
5ms to 12ms
(b): During unlock phase
Figure 12.1 Output Clock Switch Timing
No8226-15/47