LC890561W Datasheet, PDF (23/47 Pages) Sanyo Semicon Device – CMOS IC Digital Audio Interface Receiver with Built-in Data Buffer Memory

LC890561W
12.12 Input Sampling Frequency Calculation Signal Output (F0, F1, F2)
• By inputting 12.288MHz or 24.576MHz oscillation amplifier clock or external input clock, input sampling
frequencies of 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz and 192kHz are calculated and the result is
output from F0, F1 and F2.
• This processing is completed until preamble B is counted to eight after PLL is locked. Therefore, it is fixed by the
time the ERROR flag is lowered, and it will not change until PLL is unlocked.
• If the frequency other than 12.288MHz or 24.576MHz is set, the F0, F1 and F2 outputs are not guaranteed.
• This information can also be read with the microcontroller interface.
• The fs of input data except input fs free mode is within the calculation range.
Table 12.10 Fs Calculation Results when 12.288MHz or 24.576MHz is Set (Ta = 25°C, VDD = 3.3V)
F2 pin
F1 pin
F0 pin
Target fs frequency
Calculation range
L
L
L
Out of Range
-
L
L
H
32kHz
30.8kHz to 33.3kHz
L
H
L
44.1kHz
42.4kHz to 45.8kHz
L
H
H
48kHz
46.2kHz to 49.9kHz
H
L
L
88.2kHz
85.4kHz to 91.7kHz
H
L
H
96kHz
93.1kHz to 99.0kHz
H
H
L
176.4kHz
170.7kHz to 180.7kHz
H
H
H
192kHz
186.2kHz to 198.1kHz
Note: *Output when PLL is unlocked or when a sampling frequency cannot be calculated.
12.13 Validity Flag Output (VF)
• VF/DATAO2 outputs the validity flag.
• VF/DATAO2 shares the pin with the demodulated audio data output pin (delay setup is impossible). Setting as
VSEL=0 (default) makes output validity flag possible.
VF pin
L
H
Table 12.11 VF Output
Output condition
No (no burst data)
Error (possibility of burst data)
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