K4J55323QG Datasheet, PDF (9/53 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QG
256M GDDR3 SDRAM
7.3 MODE REGISTER SET(MRS)
The mode register stores the data for controlling the various operating modes of GDDR3 SDRAM. It programs CAS latency, address-
ing mode, test mode and various vendor specific options to make GDDR3 SDRAM useful for variety of different applications. The
default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for the proper opera-
tion. The mode register is written by asserting low on CS, RAS, CAS and WE (The GDDR3 SDRAM should be in active mode with CKE
already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS,
CAS and WE going low is written in the mode register. Minimum clock cycles specified as tMRD are required to complete the write oper-
ation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during
operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The Burst
length uses A0 ~ A1. CAS latency (read latency from column address) uses A2, A6 ~ A4. A7 is used for test mode. A8 is used for DLL
reset. A9 ~ A11 are used for Write latency. Refer to the table for specific codes for various addressing modes and CAS latencies.
BA1 BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
WL
DLL TM
CAS Latency
BT
CL Burst Length
BA1 BA0 An ~ A0
00
MRS
0 1 EMRS
Write Latency
A11 A10 A9
000
001
010
011
100
101
110
111
Write Latency
Reserved
1
2
3
4
5
6
7
RFU(Reserved for future use) should
stay "0" during MRS cycle
Test Mode
DLL
A8
A7 mode
0 Normal
1 Test
DLL Reset
Burst Type
A3 Burst Type
0
Sequential
1
Reserved
0
No
1
Yes
Note : DLL reset is self-clearing
CAS Latency
A2 A6 A5 A4 CAS Latency
0000
8
0001
9
0010
10
0011
11
Burst Length
A1 A0 Burst Length
00
Reserved
01
Reserved
10
4
11
8
0100
4
0101
5
0110
6
0111
7
1 0 0 0 Reserved(12)
1 0 0 1 Reserved(13)
1 0 1 0 Reserved(14)
1 0 1 1 Reserved(15)
1100
Reserved
1101
Reserved
1110
Reserved
1111
Reserved
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Rev. 1.1 November 2005