K4J55323QG Datasheet, PDF (37/53 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QG
WRITE to READ
256M GDDR3 SDRAM
T0
T1
T2
T3 T3n T4 T4n T5
T6
T10
T17
T18 T18n
/CK
CK
COMMAND
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
READ
NOP
NOP
ADDRESS
Bank
Col b
t_DQSS (NOM)
WDQS
t_DQSS
DQ
DI
b
DM
tCDLR = 5
Bank a.
Col n
CL = 8
DI
n
RDQS
t_DQSS (MIN)
WDQS
t_DQSS
DQ
DI
b
DM
RDQS
CL = 8
DI
n
t_DQSS (MAX)
WDQS
t_DQSS
DQ
DI
b
DM
CL = 8
DI
n
RDQS
NOTE :
DON’T CARE
TRANSITIONING DATA
1. DI b = data-in for column b.
2. Three subsequent elements of data-in the programmed order following DI b.
3. A burst of 4 is shown.
4. t_CDLR is referenced from the first positive CK edge after the last data-in pair.
5. The READ and WRITE commands are to the same device. However, the READ and WRITE commands may be
to different devices, in which case t_CDLR is not required and the READ command could be applied earlier.
6. A8 is LOW with the WRITE command (auto precharge is disabled).
7. WRITE latency is set to 3
37 of 53
Rev. 1.1 November 2005