K4J55323QG Datasheet, PDF (4/53 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QG
256M GDDR3 SDRAM
4.0 PIN CONFIGURATION
Normal Package (Top View)
1
2
3
4
5678
9
10
11
12
A
VDDQ VDD
VSS
ZQ
B
VSSQ DQ0
DQ1 VSSQ
C
VDDQ DQ2
DQ3 VDDQ
D
VSSQ WDQS0 RDQS0 VSSQ
E VDDQ DQ4 DM0 VDDQ
F
VDD DQ6 DQ5 CAS
G
VSS VSSQ DQ7
BA0
H
VREF
A1
RAS CKE
J
VSSA RFU1 RFU2 VDDQ
K VDDA A10
A2
A0
L
VSS VSSQ DQ25 A11
M
VDD DQ24 DQ27
A3
N _{VDDQ DQ26 DM3 VDDQ}
P _{VSSQ WDQS3 RDQS3 VSSQ}
R _{VDDQ DQ28 DQ29 VDDQ}
T _{VSSQ DQ30 DQ31 VSSQ}
V _{VDDQ VDD}
VSS
SEN
MF
VSS VDD VDDQ
VSSQ DQ9 DQ8 VSSQ
VDDQ DQ11 DQ10 VDDQ
VSSQ RDQS1 WDQS1 VSSQ
VDDQ DM1 DQ12 VDDQ
CS
DQ13 DQ14 VDD
BA1 DQ15 VSSQ VSS
WE
RFM
A5
VREF
VDDQ CK
CK VSSA
A4
A6 A8/AP VDDA
A7
DQ17 VSSQ VSS
A9
DQ19 DQ16 VDD
VDDQ DM2 DQ18 VDDQ
VSSQ RDQS2 WDQS2 VSSQ
VDDQ DQ21 DQ20 VDDQ
VSSQ DQ23 DQ22 VSSQ
RESET VSS VDD VDDQ
Note :
1. RFU1 is reserved for future use
2. RFU2 is reserved for future use
3. RFM : When the MF ball is tied LOW, RFM(H10) receiver is disabled and it recommended to be driven to a static LOW state, however,
either static HIGH or floating state on this pin will not cause any problem for the DRAM. When the MF ball is tied HIGH, RAS(H3)
becomes RFM due to mirror function and the receiver is disabled. It recommended to be driven to a static LOW state, however, either
static HIGH or floating state on this pin will not cause any problem for the DRAM
Please refer to Mirror Function Signal Mapping table at page 6.
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Rev. 1.1 November 2005