K4J55323QG Datasheet, PDF (14/53 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QG
256M GDDR3 SDRAM
7.4 EXTENDED MODE REGISTER SET(EMRS)
The extended mode register stores the data output driver strength and on-die termination options. The extended mode register is writ-
ten by asserting low on CS, RAS, CAS, WE and high on BA0(The GDDR3 SDRAM should be in all bank precharge with CKE already
high prior to writing into the extended mode register). The state of address pins A0 ~ A11 and BA0,BA1 in the same cycle as CS, RAS,
CAS and WE going low are written in the extended mode register. The minimum clock cycles specified as tMRD are required to com-
plete the write operation in the extended mode register. 4 kinds of the output driver strength are supported by EMRS (A1, A0) code. The
mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks
are in the idle state. "High" on BA0 is used for EMRS. Refer to the table for specific codes.
BA1 BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
1
Term ID RON AL tWR DLL
tWR
BA1 BA0 An ~ A0
0 0 MRS
0 1 EMRS
Vendor ID
A10 Vendor ID
0
Off
1
On
DLL
A6 DLL
0 Enable
1 Disable
ADDR/CMD Termination
A11 Termination
0
Default
1 Half of default
Default value is determined by CKE status at
the rising edge of RESET during power-up
Ron of Pull-up
A9 RON
0
40Ω
1
60Ω
Additive Latency
A8 AL
0
0
1
1
tWR
A7 A5 A4
000
001
010
011
100
101
110
111
RFU(Reserved for future use) should stay "0" during EMRS cycle
* ZQ : Resistor connection pin for On-die termination
* 1 : ALL ODT will be disabled
tWR
11
13
5
6
7
8
9
10
Termination Drive Strength
Drive Strength
A1 A0 Drive Strength
00
Autocal
01
30Ω
10
40Ω
11
50Ω
Data Termination
A3 A2 Termination
0 0 _{ODT Disabled}^*1
01
Reserved
10
ZQ/4
11
ZQ/2
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Rev. 1.1 November 2005