K4J55323QG Datasheet, PDF (25/53 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QG
256M GDDR3 SDRAM
Data Output Timing (1) - t_DQSQ, t_QH and Data Valid Window
T0
CK#
CK
RDQS ^1.6
T1
T2
T2n
T3
T3n
T4
t_CH
t_CL
t_DQSQ2 (MAX)
t_DQSQ2 (MIN)
t_DQSQ2 (MAX)
t_DQSQ2 (MIN)
DQ(Last data valid)
t_DQSH4 t_DQSL4
T2
T2n
T3
T3n
DQ(First data no longer valid)
All DQs and RDQS, collectively⁵
T2
T2n
T3
T3n
T2
t_DV4
T2n
t_DV4
T3
t_DV4
T3n
t_DV4
Data Output Timing (2) - t_DQSQ, t_QH and Data Valid Window
T0
T1
T2
T2n
T3
T3n
T4
CK#
CK
t_CH
t_CL
RDQS ^1.6
t_AC(MAX)
All DQs and RDQS, collectively⁵
RDQS ^1.6
t_AC(MIN)
t_DQSH4 t_DQSL4
T2
T2n
T3
T3n
All DQs and RDQS, collectively⁵
t_DQSH4 t_DQSL4
T2
T2n
T3
T3n
Note : 1. t_DQSQ represents the skew between the 8 DQ lines and the respective RDQS pin.
2. t_DQSQ is derived at each RDQS clock edge and is not cumulative over time and begins with first DQ transition and ends
with the last valid transition of DQs.
3. t_AC is show in the nominal case
4. t_DQHP is the lesser of tDQSL or tDQSH strobe transition collectively when a bank is active.
5. The data valid window is derived for each RDQS transitions and is defined by t_DV.
6. There are 4 RDQS pins for this device with RDQS0 in relation to DQ0-DQ7, RDQS1 in relation DQ8-DQ15, RDQS2 in
relation to DQ16-24 and RDQS3 in relation to DQ25-DQ31.
7. This diagram only represents one of the four byte lanes.
8. t_AC represents the relationship between DQ, RDQS to the crossing of CK and /CK.
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Rev. 1.1 November 2005