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K4J55323QG Datasheet, PDF (51/53 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM
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K4J55323QG
256M GDDR3 SDRAM
10.6 AC CHARACTERISTICS(I-I)
Parameter
-12
Symbol
Min Max
-14
Min Max
-16
Min Max
-20
Unit Note
Min Max
DQS out access time from CK
CK high-level width
CK low-level width
CL=11
tDQSCK -0.23 +0.23 -0.26 +0.26 -0.29 +0.29 -0.35 +0.35 ns
tCH
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
tCL
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
1.25
-
-
ns
CL=10
1.4
1.4
-
-
ns
CK cycle time
CL=9
CL=8
tCK
1.6
3.3
1.6
3.3
1.6
3.3
-
3.3 ns
2.0
2.0
2.0
-
ns
CL=7
2.0
2.0
2.0
2.0
ns
WRITE Latency
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
Active termination setup time
Active termination hold time
DQS input high pulse width
tWL
6
-
5
-
5
-
4
-
tCK 1
tDH
0.16
-
0.18
-
0.20
-
0.25
-
ns
tDS
0.16
-
0.18
-
0.20
-
0.25
-
ns
tATS
10
-
10
-
10
-
10
-
ns
tATH
10
-
10
-
10
-
10
-
ns
tDQSH 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK
DQS input low pulse widthl
tDQSL 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK
Data strobe edge to Dout edge
tDQSQ -0.140 0.140 -0.160 0.160 0.180 0.180 0.225 0.225 ns
DQS read preamble
tRPRE 0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6 tCK
DQS read postamble
tRPST 0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6 tCK
Write command to first DQS latching transition
tDQSS WL-0.2 WL+0.2 WL-0.2 WL+0.2 WL-0.2 WL+0.2 WL-0.2 WL+0.2 tCK
DQS write preamble
tWPRE 0.35
-
0.4 0.6 0.4 0.6 0.4 0.6 tCK 2
DQS write preamble setup time
tWPRES 0
-
0
-
0
-
0
-
ns
DQS write postamble
tWPST 0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6 tCK
3
Half strobe period
tCLmin
tCLmin
tCLmin
tCLmin
tHP
or
-
or
-
or
-
or
-
tCK
tCHmin
tCHmin
tCHmin
tCHmin
Data output hold time from DQS
tQH
tHP-
-
tHP-
-
tHP-
-
tHP-
-
ns
0.14
0.16
0.18
0.225
Data-out high-impedance window
from CK and /CK
Data-out low-impedance window from
CK and /CK
Address and control input hold time
tHZ
-0.3
-
-0.3
-
-0.3 -
-0.3
-
ns
4
tLZ
-0.3
-
-0.3
-
-0.3 -
-0.3
-
ns
4
tIH
0.3
-
0.35
-
0.4
-
0.5
-
ns
Address and control input setup time
tIS
0.3
-
0.35
-
0.4
-
0.5
-
ns
Address and control input pulse width
tIPW
0.9
-
1.0
-
1.1
-
1.3
-
ns
Jitter over 1~6 clock cycle error
tJ
-
0.03
-
0.03
-
0.03
-
0.03 tCK 5
Cycle to cyde duty cycle error
tDCERR -
0.03
-
0.03
-
0.03
-
0.03 tCK
Rise and fall times of CK
tR, tF
-
0.2
-
0.2
-
0.2
-
0.2 tCK
Note :
1. The WRITE latency can be set from 1 to 7 clocks. When the WRITE latency is set to 1 or 2 or 3 clocks(this case can be used regardless of frequency),
the input buffers are turned on during the ACTIVE commands reducing the latency but added power. When the WRITE latency is set to 4 ~7 clocks ,
the input buffers are turned on during the WRITE commands for lower power operation. The WRITE latency which is over 4 clocks can be used only in
case that Write Latency*tCK is greater than 7ns.
2. A low to high transition on the WDQS line is not allowed in the half clock prior to the write preamble.
3. The last rising edge of WDQS after the write postamble must be riven high by the controller. WDQS can not be pulled high by the on-die termination
alone.
4. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage
level, but specify when the device output is no longer driving (HZ) or begins driving (LZ).
5. The cycle to cycle jitter over 1~6 cycle short term jitter
51 of 53
Rev. 1.1 November 2005
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