K4J55323QG Datasheet, PDF (29/53 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QG
Random READ Accesses
T0
/CK
CK
COMMAND
READ
ADDRESS
Bank a,
Col n
RDQS
DQ
T1
T2
NOP
READ
CL = 8
Bank a,
Col b
256M GDDR3 SDRAM
T8
T8n
T9
T9n T10 T10n
NOP
NOP
NOP
DO
DO
DO
DO
DO
n
n
n
n
b
/CK
CK
COMMAND
ADDRESS
RDQS
T0
READ
Bank a,
Col n
DQ
T1
T7
NOP
READ
CL = 8
Bank a,
Col b
T8
T8n
T9
T9n T15 T15n
NOP
NOP
NOP
DO
DO
DO
DO
DO
n
n
n
n
b
DON’T CARE
TRANSITIONING DATA
NOTE :
1. DO n (or x or b or g) = data-out from column n (or column x or column x or column b or column g).
2. Burst length = 4
3. n’ or x or b’ or g’ indicates the next data-out following DO n or DO x or DO b OR DO g, respectively
4. READs are to an active row in any bank.
5. Shown with nominal t_AC and t_DQSQ.
6. RDQS will start driving high one half-clock cycle prior to the first falling edge of RDQS.
29 of 53
Rev. 1.1 November 2005