K4J55323QG Datasheet, PDF (22/53 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QG
256M GDDR3 SDRAM
7.8 Mirror Function
The GDDR3 SDRAM provides a mirror function (MF) ball to change the physical location of the control lines and all address lines
which helps to route devices back to back. The MF ball will affect RAS, CAS, WE, CS and CKE on balls H3, F4, H9, F9 and H4
respectively and A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, BA0 and BA1 on balls K4, H2, K3, M4, K9, H11, K10, L9, K11, M9,
K2, L4, G4 and G9 respectively and only detects a DC input. The MF ball should be tied directly to VSS or VDD depending on the control
line orientation desired. When the MF ball is tied low the ball orientation is as follows, RAS - H3, CAS - F4, WE - H9, CS - F9, CKE -
H4, A0 - K4, A1 - H2, A2 - K3, A3 - M4, A4 - K9, A5 - H11, A6 - K10, A7 - L9, A8 - K11, A9 - M9, A10 - K2, A11 - L4, BA0 - G4 and
BA1 - G9. The high condition on the MF ball will change the location of the control balls as follows; CS - F4, CAS - F9, RAS - H10, WE
- H4, CKE - H9, A0 - K9, A1 - H11, A2 - K10, A3 - M9, A4 - K4, A5 - H2, A6 - K3, A7 - L4, A8 - K2, A9 - M4, A10 - K11,
A11 - L9, BA0 - G9 and BA1 - G4.
Mirror Function Signal Mapping
PIN
RAS
CAS
WE
CS
CKE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA0
BA1
HIGH
H10
F9
H4
F4
H9
K9
H11
K10
M9
K4
H2
K3
L4
K2
M4
K11
L9
G9
G4
MF LOGIC STATE
LOW
H3
F4
H9
F9
H4
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
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Rev. 1.1 November 2005