K4J55323QG Datasheet, PDF (30/53 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QG
READ to WRITE
256M GDDR3 SDRAM
/CK
CK
COMMAND
ADDRESS
RDQS
T0
READ
Bank
Col n
WDQS
DQ
DM
T7
T8
T8n
T9
T9n T10
NOP
CL = 8
WRITE
Bank a,
Col b
NOP
NOP
t_WL = 4
DO
n
T11
NOP
T12 T12n
NOP
DI
b
DQ
Termination
DQ Termination Disabled
DQ Termination Enbaled
1tCK <
NOTE :
DON’T CARE
TRANSITIONING DATA
1. DO n = data-out from column n.
2. DI b = data-in from column b.
3. Burst length = 4
4. One subsequent element of data-out appears in the programmed order following DO n.
5. Data-in elements are applied following DI b in the programmed order.
6. Shown with nominal t_AC and t_DQSQ.
7. t_DQSS in nominal case.
8. RDQS will start driving high one half-clock cycle prior to the first falling edge of RDQS.
9. The gap between data termination enable to the first data-in should be greater than 1tCK
30 of 53
Rev. 1.1 November 2005