K4J55323QG Datasheet, PDF (52/53 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QG
256M GDDR3 SDRAM
AC CHARACTERISTICS (II)
Parameter
Row active time
Row cycle time
Refresh row cycle time
RAS to CAS delay for Read
RAS to CAS delay for Write
Row precharge time
Row active to Row active
Last data in to Row precharge (PRE or Auto-PRE)
Last data in to Read command
Mode register set cycle time
Auto precharge write recovery time + Precharge
Exit self refresh to Read command
Power-down exit time
Refresh interval time
-12
-14
-16
-20
Symbol
Min Max Min Max Min Max Min Max
tRAS 25 100K 22 100K 19 100K 15 100K
tRC 35
-
31
-
27
-
21
-
tRFC 45
-
39
-
31
-
27
-
tRCDR 12
-
10
-
9
-
7
-
tRCDW 8
-
6
-
5
-
4
-
tRP 10 -
9
-
8
-
6
-
tRRD 8
-
8
-
7
-
5
tWR 11
-
10
-
9
-
7
-
tCDLR 6
-
5
-
4
-
3
-
tMRD 7
-
6
-
5
-
4
-
tDAL 21
-
19
-
17
-
13
-
tXSR 20000 - 20000 - 20000 - 20000 -
tPDEX
7tCK
+tIS
-
6tCK
+tIS
-
6tCK
+tIS
-
4tCK
+tIS
-
tREF - 7.8 - 7.8 - 7.8 - 7.8
Unit Note
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
us
52 of 53
Rev. 1.1 November 2005