K4J55323QG Datasheet, PDF (33/53 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QG
WRITE Burst
256M GDDR3 SDRAM
/CK
CK
COMMAND
ADDRESS
T0
WRITE
Bank a,
Col b
T1
NOP
T2
NOP
T3 T3n T4 T4n T5 T5n T6
NOP
NOP
NOP
NOP
t_DQSS(NOM)
WDQS
t_DQSS
DQ
DbI
DM
t_DQSS(MIN)
WDQS
t_DQSS
DQ
DbI
DM
t_DQSS(MAX)
WDQS
t_DQSS
DQ
DbI
DM
NOTE :
DON’T CARE
TRANSITIONING DATA
1. DI b = data-in for column b.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. A burst of 4 is shown.
4. A8 is LOW with the WRITE command (auto precharge is disabled).
5. Write latency is set to 4
33 of 53
Rev. 1.1 November 2005