K4J55323QG Datasheet, PDF (45/53 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QG
256M GDDR3 SDRAM
9.0 COMMANDS
Below Truth table-COMMANDs provides a quick reference of available commands. This is followed by a verbal description of each
command. Two additional Truth Tables appear following the operation section : these tables provide current state/next state information.
TRUTH TABLE - COMMANDs
Name (Function)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
DATA TERMINATOR DISABLE
CS
RAS CAS
WE
ADDR
NOTES
H
X
X
X
X
8, 11
L
H
H
H
X
8
L
L
H
H
Bank/Row
3
L
H
L
H
Bank/Col
4
L
H
L
L
Bank/Col
4
L
L
H
L
Code
5
L
L
L
H
X
6, 7
L
L
L
L
Op-Code
2
X
H
L
H
X
TRUTH TABLE - DM Operation
Name (Function)
Write Enable
Write Inhibit
DM
DQS
NOTES
L
Valid
H
X
10
Note :
1. CKE is HIGH for all commands except SELF REFRESH.
2. BA0 and BA1 select either the mode register or the extended mode register (BA0=0, BA1=0 select the mode register; BA0=1, BA1=0 select
extended mode register; other combinations of BA0~BA1 are reserved). A0~A11 provide the op-code to be written to the selected mode register.
3. BA0 and BA1 provide bank address and A0~A11 provide row address.
4. BA0 and BA1 provide bank address; A0~A7 and A9 provide column address; A8 HIGH enables the auto precharge feature (nonpersistent) , and A8
LOW disables the auto precharge feature.
5. A8 LOW : BA0 and BA1 determine which banks are precharged.
A8 HIGH : All banks are precharged.
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; ll inputs and I/Os are "Don’t Care" except for CKE.
8. DESELECT and NOP are functionally interchangeable.
9. Cannot be in powerdown or self-refresh state.
10. Used to mask write data ; provided coincident with the corresponding data.
1_D1._EE_Sxc_Eep_Lt D_EA_CTA_TTermination disable.
The DESELECT function (/CS high) prevents new commands from being executed by the GDDR3(x32). The GDDR3(x32) SDRAM is
effectively deselected. Operations already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct selected GDDR3(x32) to perform a NOP (/CS LOW). This prevents
unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.
LOAD MODE REGISTER
The mode registers are loaded via inputs A0-A11. See mode register descriptions in the Register Definition section. The Load Mode
Register command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is
met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0 and
BA1 inputs selects the bank, and the address provided on inputsA0-A11 selects the row. This row remains active (or open) for
accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different
row in the same bank.
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Rev. 1.1 November 2005