K4J55323QG Datasheet, PDF (11/53 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QG
256M GDDR3 SDRAM
CAS LATENCY (READ LATENCY)
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output
data. The latency can be set to 4~15 clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will
be available nominally coincident with clock edge n+m. Below table indicates the operating frequencies at which each CAS latency set-
ting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
SPEED
-10
-11
-12
-14
-16
-20
CL=15
-
-
CAS Latency
Allowable operating frequency (MHz)
CL=14 CL=13 CL=12 CL=11 CL=10 CL=9
TBD
TBD
≤ 800
-
-
≤ 700
-
-
≤ 600
-
CL=8
-
-
-
-
CL=7
-
-
-
≤ 500
/CK
CK
COMMAND
RDQS
DQ
T0
READ
T5
T6
NOP
CL = 7
NOP
T7
T7n
NOP
/CK
CK
COMMAND
RDQS
DQ
T0
READ
T6
T7
NOP
CL = 8
NOP
T8
T8n
NOP
Burst Length = 4 in the cases shown
Shown with nominal t_AC and nominal t_DSDQ
DON’T CARE
TRANSITIONING DATA
11 of 53
Rev. 1.1 November 2005