K4J55323QG Datasheet, PDF (48/53 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QG
10.0 AC & DC OPERATING CONDITIONS
256M GDDR3 SDRAM
10.1 ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Voltage on VDDQ supply relative to Vss
MAX Junction Temperature
Storage temperature
Power dissipation
Short Circuit Output Current
Symbol
VIN, VOUT
VDD
VDDQ
TJ
TSTG
PD
IOS
Value
Unit
-0.5 ~ VDDQ + 0.5V
V
-0.5 ~ 2.5
V
-0.5 ~ 2.5
V
+125
°C
-55 ~ +150
°C
TBD
W
50
mA
Note :
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rat-
ing only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure periods may affect reliability.
10.2 POWER & DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to 0°C ≤ Tc ≤ 85°C ; VDD=1.8V + 0.1V, VDDQ=1.8V + 0.1V)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Device Supply voltage
VDD
1.7
1.8
1.9
V
1
Output Supply voltage
VDDQ
1.7
1.8
1.9
V
1
Reference voltage
VREF
0.69*VDDQ
-
0.71*VDDQ
V
2
DC Input logic high voltage
VIH (DC)
VREF+0.15
-
-
V
3
DC Input logic low voltage
VIL (DC)
-
-
VREF-0.15
V
3
Output logic low voltage
VOL(DC)
-
-
0.76
V
AC Input logic high voltage
VIH(AC)
VREF+0.25
-
-
V
3,4,5
AC Input logic low voltage
VIL(AC)
-
-
VREF-0.25
V
3,4,5
Input leakage current
Any input 0V-<VIN -< VDDQ
(All other pins not under test = 0V)
-
uA
II
-5
5
Output leakage current
IIOZ
-5
-
5
uA
(DQs are disabled ; 0V-<VOUT -< VDDQ)
Note :
1. Under all conditions, VDDQ must be less than or equal to VDD.
2. VREF is expected to equal 70% of VDDQ for the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF
may not exceed + 2 percent of the DC value. Thus, from 70% of VDDQ, VREF is allowed + 25mV for DC error and an additional +25mV for AC noise.
3. The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to maintain a valid
level. The inputs require the AC value to be achieved during signal transition edge and the driver should achieve the same slew rate through the AC
values.
4. Input and output slew rate =3V/ns. If the input slew rate is less than 3V/ns, input timing may be compromised. All slew rate are measured between
Vih and Vil. DQ and DM input slew rate must not deviate from DQS by more than 10%. If the DQ,DM and DQS slew rate is less than 3V/ns, timing is
longer than referenced to the mid-point but to the VIL(AC) maximum and VIH(AC) minimum points.
5. VIH overshoot : VIH(max) = VDDQ + 0.5V for a pulse width ≤ 500ps and the pulse width can not be greater than 1/3 of the cycle rate.
VIL undershoot : VIL(min)=0.0V for a pulse width ≤ 500ps and the pulse width can not be greater than 1/3 of the cycle rate.
48 of 53
Rev. 1.1 November 2005