K4J55323QG Datasheet, PDF (34/53 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QG
Consecutive WRITE to WRITE
T0
T1
CK#
CK
COMMAND
WRITE
NOP
ADDRESS
WDQS
Bank
Col b
t_DQSS (NOM)
DQ
DM
T2
WRITE
Bank
Col n
256M GDDR3 SDRAM
T3 T3n T4 T4n T5 T5n T6 T6n T7
NOP
NOP
NOP
NOP
NOP
DI
DI
b
n
DON’T CARE
TRANSITIONING DATA
NOTE :
1. DI b, etc. = data-in for column b, etc.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. Three subsequent elements of data-in are applied in the programmed order following DI n.
4. Burst of 4 is shown.
5. Each WRITE command may be to any bank of the same device.
6. Write latency is set to 3
34 of 53
Rev. 1.1 November 2005