K4J55323QG Datasheet, PDF (13/53 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QG
256M GDDR3 SDRAM
TEST MODE
The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7 set to zero, and bits A0-A6 and A8-
A11 set to the desired values. Test mode is entered by issuing a MODE REGISTER SET command with bit A7 set to one, and bits A0-
A6 and A8-A11 set to the desired values. Test mode functions are specific to each Dram Manufacturer and its exact functions are hidden
from the user.
DLL RESET
The normal operating mode is selected by issuing a MODE REGISTER SET command with bit A7 set to zero, and bits A0-A6 and A8-
A11 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bit A8 set to one, and bits A0-
A7 and A9-A11 set to the desired values. When a DLL Reset is complete the GDDR3 SDRAM reset bit 8 of the mode register to a zero.
After DLL Reset MRS, Power down can not be issued within 10 clock.
In case the clock frequency need to be changed after the power-up, 256Mb GDDR3 doesn’t require DLL reset. Instead, DLL should
be disabled first before the frequency changed and then change the clock frequency as needed. After the clock frequency changed,
there needed some time till clock become stable and then enable the DLL and then 20K cycle required to lock the DLL
Clock frequency change sequence after the power-up(example)
CK,CK
700Mbps
1000Mbps
Command
EMRS
DLL Disable
Wait until
clock stable
EMRS
DLL Enable
20K cycle for
DLL locking time
Any
Command
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Rev. 1.1 November 2005