K4J55323QG Datasheet, PDF (46/53 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QG
256M GDDR3 SDRAM
READ
The READ command is used to initiate a burst read access to an active row. The value on the BA0 and BA1 inputs select the bank, and
the address provided on inputs A0-A7, A9 selects the starting column location. The value on input A8 determines whether or not auto
precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto pre-
charge is not selected, the row will remain open for subsequent accesses.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value on the BA0 and BA1 inputs select the bank,
and the address provided on inputs A0-A7, A9 selects the starting column location. The value on inputs A8 determines whether or not
auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto
precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory
array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW. the corresponding
data will be written to memory; If the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not
be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be
available for a subsequent row access a specified time (t_RP) after the PRECHARGE command is issued. Input A8 determines whether
one or all banks are to be precharged, and in the case where only one banks are to be precharged, inputs BA0,BA1 select the bank.
Otherwise BA0, BA1 are treated as "Don’t Care." Once a bank has been precharged, it is in the idle state and must be activated prior
to any READ or WRITE command will be treated as a NOP if there is no open row is already in the process of precharging.
AUTO PRECHARGE
Auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an
explicit command. This is accomplished by using A8 to enable auto precharge in conjunction with a specific READ or WRITE com-
mand. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion
of the READ or WRITE burst. Auto precharge is non persistent in that it is either enable or disabled for each individual READ or WRITE
command. Auto precharge ensures that the precharge is initiated at the earliest valid state within a burst. This "earliest valid stage" is
determined as if an explicit PRECHARGE command was issued at the earliest possible time, without violating t_RAS(min), as described
for each burst type in the Operation section of this data sheet. The user must not issue another command to the same bank until the
precharge time(t_RP) is completed.
AUTO REFRESH
Auto Refresh is used during normal operation of the GDDR3 SDRAM and is analogous to /CAS-BEFORE-/RAS (CBR) REFRESH in
FPM/EDO DRAMs. This command is non persistent, so it must be issued each time a refresh is required. The addressing is generated
by the internal refresh controller. This makes the address bits a "Don’t Care" during an Auto Refresh command. The 256Mb(x32)
GDDR3 requires Auto Refresh cycles at an average interval of 3.9us (maximum).
A maximum Auto Refresh commands can be posted to any given GDDR3(x32) SDRAM, meaning that the maximum absolute interval
between any Auto Refresh command and the next Auto Refresh command is 9 x 3.9us(35.1us). This maximum absolute interval is to
allow GDDR3(x32) SDRAM output drivers and internal terminators to automatically re calibrate compensating for voltage and tempera-
ture changes.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the GDDR3(x32) SDRAM ,even if the rest of the system is powered
down. When in the self refresh mode,the GDDR3(x32) SDRAM retains data without external clocking. The SELF REFRESH command
is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF
REFRESH and is automatically enabled and reset upon exiting SELF REFRESH. The active termination is also disabled upon entering
Self Refresh and enabled upon exiting Self Refresh. (20K clock cycles must then occur before a READ command can be issued). Input
signals except CKE are "Don’t Care" during SELF REFRESH. The procedure for exiting self refresh requires a sequence of commands.
First, CK and /CK must be stable prior to CKE going back HIGH. Once CKE is HIGH,the GDDR3(x32) must have NOP commands
issued for tXSNR because tine is required for the completion of any internal refresh in progress. A simple algorithm for meeting both
refresh, DLL requirements and out-put calibration is to apply NOPs for 20K clock cycles before applying any other command to allow
the DLL to lock and the output drivers to recalibrate.
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Rev. 1.1 November 2005