K4J55323QG Datasheet, PDF (6/53 Pages) Samsung semiconductor – 256Mbit GDDR3 SDRAM

K4J55323QG
6.0 BLOCK DIAGRAM (2Mbit x 32I/O x 4 Bank)
WDQS
256M GDDR3 SDRAM
Bank Select
Input Buffer
32
Input Buffer
Data Input Register
Serial to parallel
128
LWE
LDMi
iCK
ADDR
2M x 32
2M x 32
2M x 32
2M x 32
128
32
x32
DQi
Column Decoder
Latency & Burst Length
LCKE
LRAS LCBR LWE
LCAS
Programming Register
LWCBR
Timing Register
Output
DLL
CK,CK
LDMi
RDQS
iCK CKE CS RAS CAS WE DMi
* iCK : internal clock
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Rev. 1.1 November 2005