4501_M Datasheet, PDF (90/212 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4501 Group
HARDWARE
INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAB2 (Transfer data to Accumulator and register B from timer 2)
Instruction
code
D9
D0
Number of
1001110001
271
2
16
words
1
Number of
cycles
1
Flag CY
–
Skip condition
–
Operation:
(B) ← (T27–T24)
(A) ← (T23–T20)
Grouping:
Description:
Timer operation
Transfers the high-order 4 bits (T27–T24) of
timer 2 to register B.
Transfers the low-order 4 bits (T23–T20) of
timer 2 to register A.
TABAD (Transfer data to Accumulator and register B from register AD)
Instruction
code
D9
D0
Number of
1001111001
279
2
16
words
1
Number of
cycles
1
Flag CY
–
Skip condition
–
Operation:
In A/D conversion mode (Q13 = 0),
(B) ← (AD9–AD6)
(A) ← (AD5–AD2)
In comparator mode (Q13 = 1),
(B) ← (AD7–AD4)
(A) ← (AD3–AD0)
(Q13 : bit 3 of A/D control register Q1)
Grouping:
Description:
A/D conversion operation
In the A/D conversion mode (Q13 = 0), trans-
fers the high-order 4 bits (AD9–AD6) of register
AD to register B, and the middle-order 4 bits
(AD5–AD2) of register AD to register A. In the
comparator mode (Q13 = 1), transfers the high-
order 4 bits (AD7–AD4) of comparator register
to register B, and the low-order 4 bits (AD3–
AD0) of comparator register to register A.
TABE (Transfer data to Accumulator and register B from register E)
Instruction
code
D9
D0
Number of Number of Flag CY
0000101010 02A
words
cycles
2
16
1
1
–
Skip condition
–
Operation:
(B) ← (E7–E4)
(A) ← (E3–E0)
Grouping:
Description:
Register to register transfer
Transfers the high-order 4 bits (E7–E4) of
register E to register B, and low-order 4 bits
of register E to register A.
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
Instruction
code
D9
D0
Number of Number of Flag CY
0
0
1
0
0
p4 p3 p2 p1 p0
2
0
8
+p
p
16
words
1
cycles
3
–
Skip condition
–
Operation:
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Grouping:
Description:
Note:
Arithmetic operation
Transfers bits 7 to 4 to register B and bits 3 to
0 to register A. These bits 7 to 0 are the ROM
pattern in ad-dress (DR2 DR1 DR0 A3 A2 A1
A0)2 specified by registers A and D in page p.
p is 0 to 15 for M34501M2, and p is 0 to 31
for M34501M4/E4.
When this instruction is executed, be careful
not to over the stack because 1 stage of
stack register is used.
Rev.2.01 Feb 07, 2005
REJ09B0192-0201
1-78