4501_M Datasheet, PDF (109/212 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4501 Group
HARDWARE
INSTRUCTIONS
Skip condition
Datailed description
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V10 = 0: (EXF0) = 1
(INT) = “L”
However, I12 = 0
(INT) = “H”
However, I12 = 1
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– Clears (0) to interrupt enable flag INTE, and disables the interrupt.
– Sets (1) to interrupt enable flag INTE, and enables the interrupt.
– When V10 = 0 : Skips the next instruction when external 0 interrupt request flag EXF0 is “1.” After skipping,
clears (0) to the EXF0 flag. When the EXF0 flag is “0,” executes the next instruction.
When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register
V1)
– When I12 = 0 : Skips the next instruction when the level of INT pin is “L.” Executes the next instruction when
the level of INT pin is “H.”
When I12 = 1 : Skips the next instruction when the level of INT pin is “H.” Executes the next instruction when
the level of INT pin is “L.” (I12: bit 2 of interrupt control register I1)
– Transfers the contents of interrupt control register V1 to register A.
– Transfers the contents of register A to interrupt control register V1.
– Transfers the contents of interrupt control register V2 to register A.
– Transfers the contents of register A to interrupt control register V2.
– Transfers the contents of interrupt control register I1 to register A.
– Transfers the contents of register A to interrupt control register I1.
– Transfers the contents of timer control register W1 to register A.
– Transfers the contents of register A to timer control register W1.
– Transfers the contents of timer control register W2 to register A.
– Transfers the contents of register A to timer control register W2.
– Transfers the contents of timer control register W6 to register A.
– Transfers the contents of register A to timer control register W6.
– Transfers the high-order 4 bits (T17–T14) of timer 1 to register B.
Transfers the low-order 4 bits (T13–T10) of timer 1 to register A.
– Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1. Trans-
fers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1.
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– Transfers the high-order 4 bits (T27–T24) of timer 2 to register B.
Transfers the low-order 4 bits (T23–T20) of timer 2 to register A.
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– Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2. Trans-
fers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2.
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V12 = 0: (T1F) = 1
V13 = 0: (T2F) =1
– Transfers the contents of register B to the high-order 4 bits (R17–R14) of reload register R1, and the con-
tents of register A to the low-order 4 bits (R13–R10) of reload register R1.
– When V12 = 0 : Skips the next instruction when timer 1 interrupt request flag T1F is “1.” After skipping,
clears (0) to the T1F flag. When the T1F flag is “0,” executes the next instruction.
When V12 = 1 : This instruction is equivalent to the NOP instruction. (V12: bit 2 of interrupt control register V1)
– When V13 = 0 : Skips the next instruction when timer 1 interrupt request flag T2F is “1.” After skipping,
clears (0) to the T2F flag. When the T2F flag is “0,” executes the next instruction.
When V13 = 1 : This instruction is equivalent to the NOP instruction. (V13: bit 3 of interrupt control register V1)
Rev.2.01 Feb 07, 2005
REJ09B0192-0201
1-97