4501_M Datasheet, PDF (11/212 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4501 Group
List of tables
List of tables
CHAPTER 1 HARDWARE
Table Selection of system clock .................................................................................................. 1-7
Table 1 ROM size and pages .................................................................................................... 1-17
Table 2 RAM size ........................................................................................................................ 1-18
Table 3 Interrupt sources ............................................................................................................ 1-19
Table 4 Interrupt request flag, interrupt enable bit and skip instruction .............................. 1-19
Table 5 Interrupt enable bit function ......................................................................................... 1-19
Table 6 Interrupt control registers ............................................................................................. 1-21
Table 7 External interrupt activated conditions ........................................................................ 1-23
Table 8 External interrupt control register ................................................................................ 1-24
Table 9 Function related timers ................................................................................................. 1-26
Table 10 Timer control registers ................................................................................................ 1-28
Table 11 A/D converter characteristics ..................................................................................... 1-33
Table 12 A/D control registers ................................................................................................... 1-34
Table 13 Change of successive comparison register AD during A/D conversion .............. 1-35
Table 14 Port state at reset ....................................................................................................... 1-39
Table 15 Functions and states retained at RAM back-up ..................................................... 1-42
Table 16 Return source and return condition .......................................................................... 1-43
Table 17 Key-on wakeup control register ................................................................................. 1-45
Table 18 Pull-up control register and interrupt control register ............................................ 1-46
Table 19 Clock control register MR .......................................................................................... 1-49
Table 20 Product of built-in PROM version ........................................................................... 1-104
CHAPTER 2 APPLICATION
Table 2.1.1 Key-on wakeup control register K0 ........................................................................ 2-5
Table 2.1.2 Pull-up control register PU0 .................................................................................... 2-5
Table 2.1.3 Key-on wakeup control register K1 ........................................................................ 2-6
Table 2.1.4 Pull-up control register PU1 .................................................................................... 2-6
Table 2.1.5 Key-on wakeup control register K2 ........................................................................ 2-7
Table 2.1.6 Pull-up control register PU2 .................................................................................... 2-7
Table 2.1.7 Timer control register W6 ........................................................................................ 2-8
Table 2.1.8 Connections of unused pins .................................................................................. 2-11
Table 2.2.1 Interrupt control register V1 ................................................................................... 2-13
Table 2.2.2 Interrupt control register V2 ................................................................................... 2-14
Table 2.2.3 Interrupt control register I1 .................................................................................... 2-15
Table 2.3.1 Interrupt control register V1 ................................................................................... 2-22
Table 2.3.2 Timer control register W1 ...................................................................................... 2-22
Table 2.3.3 Timer control register W2 ...................................................................................... 2-23
Table 2.3.4 Timer control register W6 ...................................................................................... 2-23
Table 2.3.5 Recommended operating condition of pulse width input to CNTR pin ........... 2-32
Table 2.4.1 A/D control register Q1 .......................................................................................... 2-34
Table 2.4.2 Recommended operating conditions (when using A/D converter) ................... 2-37
Table 2.7.1 Functions and states retained at RAM back-up mode ...................................... 2-42
Table 2.7.2 Return source and return condition ...................................................................... 2-43
Table 2.7.3 Start condition identification ................................................................................... 2-43
Table 2.7.4 Key-on wakeup control register K0 ...................................................................... 2-44
Table 2.7.5 Key-on wakeup control register K1 ...................................................................... 2-44
Table 2.7.6 Key-on wakeup control register K2 ...................................................................... 2-45
Rev.2.01 Feb 07, 2005
vii
REJ09B0192-0201