4501_M Datasheet, PDF (198/212 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4501 Group
APPENDIX
3.3 List of precautions
Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared to “0”, the RAM back-up mode is selected and the input of
INT pin is disabled, be careful about the following notes.
• When the key-on wakeup function of port P13 is not used (register K13 = “0”), clear bits 2 and 3
of register I1 before system enters to the RAM back-up mode. (refer to Figure 3.3.2 ➀).
LA
TI1A
DI
EPOF
POF
0 ; (00✕✕2)
; Input of INT disabled .................... ➀
; RAM back-up
✕ : these bits are not used here.
Fig. 3.3.2 External 0 interrupt program example-2
Note [3] on bit 2 of register I1
When the interrupt valid waveform of the P13/INT pin is changed with the bit 2 of register I1 in
software, be careful about the following notes.
• Depending on the input state of the P13/INT pin, the external 0 interrupt request flag (EXF0) may
be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 3.3.3 ➀) and then, change the bit 2
of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one
instruction (refer to Figure 3.3.3 ➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer
to Figure 3.3.3 ➂).
LA 4 ; (✕✕✕02)
TV1A ; The SNZ0 instruction is valid ..... ➀
LA 12 ; (✕1✕✕2)
TI1A
; Interrupt valid waveform is changed
NOP
........................................................... ➁
SNZ0 ; The SNZ0 instruction is executed
(EXF0 flag cleared)
NOP
........................................................... ➂
✕ : these bits are not used here.
Fig. 3.3.3 External 0 interrupt program example-3
(6) Power down instruction
Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction.
Rev.2.01 Feb 07, 2005
REJ09B0192-0201
3-29