4501_M Datasheet, PDF (145/212 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4501 Group
APPLICATION
2.3 Timers
➀ Disable Interrupts
Timer 2 interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
All interrupts disabled (DI instruction)
Interrupt control register V1
b3
0
✕
✕
b0
✕
Timer 2 interrupt occurrence
(TV1A instruction)
disabled
➁ Stop Timer Operation
Timer operation is temporarily stopped.
Timer 2 count source is selected.
Timer control register W2
b3
0✕
1
b0
0
Timer 2 stop (TW2A instruction)
CNTR input selected for count source
➂ Set Timer Value
Timer 2 count time is set.
Timer 2 reload register R2 “6316”
Timer count value 99 set (T2AB instruction)
➃ Set port P12
P12/CNTR I/O port is set to input port.
b3
b0
Output latch of port P12 ✕ 1 ✕ ✕ Input mode is set. (OP1A instruction)
b3
b0
Timer control register W6 ✕ ✕ ✕ 0 Port P12 (I/O) set (TW6A instruction)
➄ Clear Interrupt Request
Timer 2 interrupt activated condition is cleared.
Timer 2 interrupt request flag T2F “0”
Timer 2 interrupt activated condition cleared
(SNZT2 instruction)
Note when the interrupt request is cleared
When ➄ is executed, considering the skip of the next instruction according to the
interrupt request flag T2F, insert the NOP instruction after the SNZT2 instruction.
➅ Start Timer 2 Operation
Timer 2 temporarily stopped is restarted.
b3
b0
Timer control register W2 1 ✕ 1 0
Timer 2 operation start (TW2A instruction)
➆ Enable Interrupts
The timer 2 interrupt which is temporarily disabled is enabled.
Interrupt control register V1
b3
b0
1✕✕✕
Timer 2 interrupt occurrence enabled
(TV1A instruction)
Interrupt enable flag INTE “1”
All interrupts enabled (EI instruction)
“✕”: it can be “0” or “1.”
Fig. 2.3.5 CNTR input setting example
However, specify the pulse width input to CNTR pin. Refer to section “2.3.4 Notes on use” for the timer
external input period condition.
Rev.2.01 Feb 07, 2005
REJ09B0192-0201
2-28